ADCMP603| Datasheet

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Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator ADCMP603
FEATURES
Fully specified rail to rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage Complementary outputs 3.5 ns propagation delay 12 mW at 3.3 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 50 dB -40 C to +125 C operation

FUNCTIONAL BLOCK DIAGRAM
VCCI VCCO

VP NONINVERTING INPUT

Q OUTPUT

ADCMP603
VN INVERTING INPUT

TTL Q OUTPUT

LE/HYS INPUT SDN INPUT

APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)

Figure 1.

GENERAL DESCRIPTION
The ADCMP603 is a very fast comparator fabricated on XFCB2, an Analog Devices, Inc. proprietary process. This comparator is exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.2 V, low noise complementary TTL-/CMOS-compatible output drivers, latch inputs with adjustable hysteresis and a shutdown input. The device offers 3.5 ns propagation delay with 10 mV overdrive on 4 mA typical supply current. A flexible power supply scheme allows the device to operate with a single +2.5 V positive supply and a -0.5 V to +2.8 V input signal range up to a +5.5 V positive supply with a -0.5 V to +5.8 V input signal range. Split input/output supplies with no sequencing restrictions support a wide input signal range while still allowing independent output swing control and power savings. The device passes 4.5 kV HBM ESD testing and the absolute maximum ratings include current limits for all pins. The complementary TTL-/CMOS-compatible output stage is designed to drive up to 5 p
F with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. Latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP603 is available in a 12-lead LFCSP package.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

05915-001