ADF4156| Datasheet

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6 GHz Fractional-N Frequency Synthesizer ADF4156
FEATURES
RF bandwidth to 6 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113/ADF4106/ ADF4153 and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADISimPLL Cycle slip reduction for faster lock times

GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a sigma-delta (-) based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry leading to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.

APPLICATIONS
CATV equipment Base stations for mobile radio (WiMAX, GSM, PCS, DCS, SuperCell 3G, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, PMR Communications test equipment

FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP RSET

ADF4156
REFIN 2 DOUBLER 5-BIT R COUNTER /2 DIVIDER VDD DGND LOCK DETECT MUXOUT OUTPUT MUX SDOUT VDD RDIV NDIV THIRD ORDER FRACTIONAL INTERPOLATOR FRACTION REG MODULUS REG INTEGER REG N COUNTER CURRENT SETTING RFCP4 RFCP3 RFCP2 RFCP1 RFINA RFINB + PHASE FREQUENCY DETECTOR REFERENCE

CHARGE PUMP CSR

HIGH Z

CE CLOCK DATA LE

32-BIT DATA REGISTER

AGND

DGND

CPGND

Figure 1.

Rev. 0
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