ADSP-21160N| Datasheet

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SUMMARY High Performance 32-Bit DSP--Applications in Audio, Medical, Military, Graphics, Imaging, and Communication Super Harvard Architecture--Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Backwards Compatible--Assembly Source Level Compatible with Code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) Computational Architecture--Two 32-Bit IEEE Floating-Point Computation Units, Each with a Multiplier, ALU, Shifter, and Register File

S DSP Microcomputer ADSP-21160N
Integrated Peripherals--Integrated I/O Processor, 4 M Bits On-Chip Dual-Ported SRAM, Glueless Multiprocessing Features, and Ports (Serial, Link, External Bus, and JTAG) KEY FEATURES 100 MHz (10 ns) Core Instruction Rate Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing Zero-Overhead Looping and Single-Cycle Loop Setup, Providing Efficient Program Sequencing

FUNCTIONAL BLOCK DIAGRAM

CORE PROCESSOR TIMER INSTRUCTION CACHE 32 48-BIT

DUAL-PORTED SRAM TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT ADDR DATA ADDR DATA
BLOCK 0

JTAG
BLOCK 1

6 TEST AND EMULATION

I/O PORT DATA ADDR DATA ADDR

DAG2 DAG1 4 32 8 4 32

PROGRAM SEQUENCER 32 IOD 64 IOA 18 EXTERNAL PORT ADDR BUS MUX MULTIPROCESSOR INTERFACE DATA BUS MUX HOST PORT 64 32

PM ADDRESS BUS DM ADDRESS BUS

PM DATA BUS BUS CONNECT (PX) DM DATA BUS

16/32/40/48/64 32/40/64

MULT

DATA REGISTER FILE (PEX) 16 40-BIT

BARREL SHIFTER

DATA REGISTER FILE (PEY) 16 40-BIT

MULT

IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS AND DATA BUFFERS

DMA CONTROLLER SERIAL PORTS (2) LINK PORTS (6)

4 6 6 60

ALU

I/O PROCESSOR

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