ADSP-2184N| Datasheet

ADSP-2184N, ADSP-2185N, ADSP-2186N, ADSP-2187N, ADSP-2188N, ADSP-2

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PERFORMANCE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sustained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode

DSP Microcomputer ADSP-218xN Series
SYSTEM INTERFACE FEATURES
Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation All inputs tolerate up to 3.6 V regardless of mode 16-bit internal DMA port for high-speed access to on-chip memory (mode selectable) 4M-byte memory interface for storage of data tables and program overlays (mode selectable) 8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable) Programmable memory strobe and separate I/O memory space permits "glueless" system design Programmable wait state generation Two double-buffered serial ports with companding hardware and automatic data buffering Automatic booting of on-chip program memory from bytewide external memory, for example, EPROM, or through internal DMA Port Six external interrupts 13 programmable flag pins provide flexible system signaling UART emulation through software SPORT reconfiguration ICE-PortTM emulator interface supports debugging in final systems

INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 256K byte of on-chip RAM, configured Up to 48K words program memory RAM Up to 56K words data memory RAM Dual-purpose program memory for both instruction and data storage Independent ALU, multiplier/accumulator, and barrel shifter computational units Two independent data address generators Powerful program sequencer provides zero overhead looping conditional instruction execution Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA

PO W E R-DO WN C ONTR O L FU L L M EM O R Y M O D E M EM OR Y D A T A A D D RES S G ENERAT OR S D A G1 D AG2 PROG RAM SEQ U ENCER PRO GRA M ME M ORY UP TO 48K 24-B IT D A TA ME M ORY UP TO 56K 16-B IT PROG RA MM ABL E I/O AND F LA GS EX TE RNAL AD D R ES S BUS EX TE RNAL D A TA BUS BY TE DM A C ON T R OLL ER OR EX TE RNAL D A TA BUS T IM ER INTER NA L DMA P ORT H OS T M OD E

P R O GR A M M EM O R Y AD D R ES S D ATA M EM O RY A D D R ES S PR O GRAM M EMO R Y DATA DA TA M E M OR Y DA TA

A R ITH M ETIC UN ITS A LU MAC S H IFTE R

S ER IAL PO R TS S POR T0 SPOR T 1

A DS P-2100 B AS E A RC H IT EC T UR E

Figure 1. Functional Block Diagram
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Rev. A
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