OP07| Datasheet

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

Ultralow Offset Voltage Operational Amplifier OP07
FEATURES
Low VOS: 75 V maximum Low VOS drift: 1.3 V/ C maximum Ultrastable vs. time: 1.5 V per month maximum Low noise: 0.6 V p-p maximum Wide input voltage range: 14 V typical Wide supply voltage range: 3 V to 18 V 125 C temperature-tested dice

PIN CONFIGURATION
VOS TRIM IN +IN V
1 2 3 4

OP07

8 7 6 5

VOS TRIM V+ OUT
00316-001

NC = NO CONNECT

Figure 1.

APPLICATIONS
Wireless base station control circuits Optical network control circuits Instrumentation Sensors and controls Thermocouples Resistor thermal detectors (RTDs) Strain bridges Shunt current measurements Precision filters

GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75 V maximum for OP07E) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current ( 4 nA for the OP07E) and high open-loop gain (200 V/mV for the OP07E). The low offset and high open-loop gain make the OP07 particularly useful for high gain instrumentation applications.

The wide input voltage range of 13 V minimum combined with a high CMRR of 106 dB (OP07E) and high input impedance provide high accuracy in the noninverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variations in temperature is excellent. The accuracy and stability of the OP07, even at high gain, combined with the freedom from external nulling have made the OP07 an industry standard for instrumentation applications. The OP07 is available in two standard performance grades. The OP07E is specified for operation over the 0 C to 70 C range, and the OP07C is specified over the -40 C to +85 C temperature range. The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow SOIC packages. For CERDIP and TO-99 packages and standard microcircuit drawing (SMD) versions, see the OP77.

V+ 7 R2A1 R1A 1 R2B1 (OPTIONAL NULL) C1 8 R1B Q19 Q9 Q7 NONINVERTING INPUT 3 INVERTING INPUT R3 Q5 Q3 Q1 Q21 R4 2 4 V
1 R2A

Q10 Q11 Q12 C2 Q17

R9 OUT 6 Q16 Q15 R10 Q20

Q8 Q6 Q4 Q27 C3 R5 Q26 Q2 Q25

Q23 Q24

Q22

Q14 Q13 R6

Q18 R8
00316-002

AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.

Figure 2. Simplified Schematic

Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.