AT76C712| Datasheet

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Features
Advanced RISC Architecture, 130 Powerful Instructions, most Single Clock Cycle
Execution

JTAG (IEEE std. 1149.1 compliant) Interface
Boundary-Scan Capabilities According to the JTAG Standard Extensive On-Chip Debug Support Clock Generator Provides CPU Rates Up to 48MHz Only One External Clock Crystal of 12MHz can generate all the required System Clocks: Internal Clock for Standard UART Rates A 48MHz and 96MHz clock for USB Data Recovery AVR Processor and System Clock. On Chip Bootstrap ROM Provides a Variety of Firmware Upgrade Modes Device Firmware Upgrade through USB for the internal Program SRAM (No External Non-Volatile SPI Memory Required) Device Firmware Upgrade through USB for both the internal Program SRAM and the External SPI DataFlash or EEPROM or Serial Flash. SPI Program Mode from the External DataFlash or EEPROM or Serial Flash. Two On Chip 16550 UARTs Supporting Baud Rates Up to 921Kbaud. Both UARTs incorporate individual Transmit and Receive FIFOs of 16 Bytes UART0 Supports Modem Control Signals Programmable SPI interface Full-Speed USB Interface (12Mbit/s) 2.0 Compliant DMA Channels allow fast data tra
nsfers between Endpoint Buffers and internal SRAM. The DMA transfer rate is 12MHz for all channels. 8K x 16bits (Up to 11K x 16bits), in-system SRAM for Program Code (Program Memory) On Chip 8KBytes SRAM. Default use of this memory is for Data and Variables. You can configure 2, 4 or 6Kbyte to be remapped for program storage in the Address Area above the Program Memory. Thus, reallocating 6KBytes, the Program Space becomes 11K x 16bits and the Data Space 2KBytes. Two 8-bit Timer/Counters One 16-bit Timer/Counter Two External interrupts Through GPIOs Programmable Watchdog Timer Low voltage operation: 1.8V for the Core, 1.8V or 3.3V for the periphery 3.3V for the USB. Low cost 64-pin leadfree TQFP Package, suitable for USB-to-UART Bridge Applications

High Speed (48MHz) AVR based Bridging Device AT76C712

5635AX USB 10/06