AT91SAM7A3__Preliminary| Datasheet

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Features
Incorporates the ARM7TDMI ARM Thumb Processor
High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt EmbeddedICETM In-circuit Emulation, Debug Communication Channel Support 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes Single Cycle Access at Up to 30 MHz in Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities 32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) Embedded Flash Controller, Abort Status and Misalignment Detection Memory Protection Unit Reset Controller (RSTC) Based on Three Power-on Reset Cells Provides External Reset Signal Shaping and Reset Sources Status Clock Generator (CKGR) Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL Power Management Controller (PMC) Power Optimization
Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle Mode, Standby Mode and Backup Mode Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART and Support for Debug Communication Channel interrupt Periodic Interval Timer (PIT) 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) 12-bit key-protected Programmable Counter Provides Reset or Interrupt Signal to the System Counter May Be Stopped While the Processor is in Debug Mode or in Idle State Real-time Timer (RTT) 32-bit Free-running Counter with Alarm Runs Off the Internal RC Oscillator Two Parallel Input/Output Controllers (PIO) Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Input Change Interrupt Capability on Each I/O Line Individually Programmable
Open-drain, Pull-up resistor and Synchronous Output Shutdown Controller (SHDWC) Programmable Shutdown Pin and Wake-up Circuitry Two 32-bit Battery Backup Registers for a Total of 8 Bytes One 8-channel 20-bit PWM Controller (PWMC) One USB 2.0 Full Speed (12 Mbits per Second) Device Port On-chip Transceiver, 2376-byte Configurable Integrated FIFOs

AT91 ARM Thumb-based Microcontrollers AT91SAM7A3 Preliminary

6042E ATARM 14-Dec-06