ATF22LV10C| Datasheet

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Features

3.0V to 5.5V Operating Range Advanced Low-voltage Electrically-erasable Programmable Logic Device User-controlled Power-down Pin Option Pin-controlled Standby Power (10 uA Typical) Well-suited for Battery Powered Systems 10 ns Maximum Propagation Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Hold Inputs to Previous Logic States Advanced Electrically-erasable Technology Reprogrammable 100% Tested High-reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts Inputs are 5V Tolerant True Input Transition Detection "QZ" Version Green Package Options (Pb/Halide-free/RoHS Compliant) Available

Highperformance EE PLD ATF22LV10C
See separate datasheet for ATF22LV10CQZ option.

1. Description
The ATF22LV10C is a high-performance CMOS (electrically-erasable) programmable logic device (PLD) that utilizes Atmel's proven electrically-erasable Flash memory technology. Speeds down to 10 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10C provides a low-voltage and user controlled "zero" power CMOS PLD solution. A user-controlled power-down feature offers "zero" (5 mA typical) standby power. This feature allows the user to manage total system power to meet specific application requirements and enhance reliability, all without sacrificing speed. (The ATF22LV10CZ provides edge-sensing "zero" standby power (10 mA typical), as well as low voltage operation. See the ATF22LV10CZ datasheet.) The ATF22LV10C is capable of operating at supply voltages down to 3.0V. When the power-down pin is active, the device is placed into a zero standby power-down mode. When the power-down pin is not us
ed or active, the device operates in a full power low voltage mode. Pin "keeper" circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The ATF22LV10C macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly-complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power-up. Register preload simplifies testing. A security fuse prevents unauthorized copying of programmed fuse patterns.

0780L PLD 12/05