TSC695FL| Datasheet

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Features
Integer Unit Based on SPARC V7 High-performance RISC Architecture Optimized Integrated 32/64-bit Floating-point Unit On-chip Peripherals
EDAC and Parity Generator and Checker Memory Interface Chip Select Generator Waitstate Generation Memory Protection DMA Arbiter Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) Interrupt Controller With 5 External Inputs General Purpose Interface (GPI) Dual UART Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes Fully Static Design Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz Core Consumption: 0.3W Typ. at 12 MIPs Operating Range: 3.15V to 3.45V -55 C to +125 C Tested up to a Total Dose of 300 Krds (si) according toMIL STD 883 Method 1019 No Single Event Latch-up Below an LET Threshold of 80 MeV/mg/cm2 Single Event Upsets Error Rate Better than: 2 E-7 Error/Component/Day in GEO Orbit 5 E-5 Error/Component/Day in LEO Orbit (53 , 1000 km) Quality Grades: ESCC, and QMLQ or V with 5962-03246 Package: 256 MQFPF; Bare Die

Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor TSC695FL

Description
The TSC695FL (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications. The processor is manufactured using the Atmel 0.5 um radiation tolerant ( 300 KRADs (Si)) CMOS enhanced process (RTP). It can operate at a low voltage for optimized power consumption (see datasheet TSC695FL). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection. The TSC695FL includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695FL offers a high security watchdog, two timers, an interrupt controller, parallel and serial interfaces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly te
stable with the support of an On-Chip Debugger (OCD), and a boundary scan through JTAG interface. The TSC695FL is a selection of the TSC5695F performed for a narrow 3.3V biasing voltage range ( 0.15V), as such, this specification can be only met by the products solds as TSC695FL. Where computing power is not the key factor, it allows for a dramatic power consumption reduction (70%).

Rev. 4204C AERO 05/05