100302

100302 Low Power Quint 2-Input OR/NOR Gate

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100302 Low Power Quint 2-Input OR/NOR Gate

August 1989 Revised August 2000

100302 Low Power Quint 2-Input OR/NOR Gate
General Description
The 100302 is a monolithic quint 2-input OR/NOR gate with common enable. All inputs have 50 k pull-down resistors and all outputs are buffered.

Features
s 43% power reduction of the 100102 s 2000V ESD protection s Pin/function compatible with 100102 s Voltage compensated operating range -4.2V to -5.7V s Available to industrial grade temperature range (PLCC package only)

Ordering Code:
Order Number 100302SC 100302PC 100302QC 100302QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40 C to 85 C)

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Connection Diagrams
24-Pin DIP/SOIC 28-Pin PLCC

Pin Descriptions
Pin Names Dna Dne E Oa Oe Oa Oe Data Inputs Enable Input Data Outputs Complementary Data Outputs Description

2000 Fairchild Semiconductor Corporation

DS010580

www.fairchildsemi.com