100331

100331 Low Power Triple D-Type Flip-Flop

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

100331 Low Power Triple D-Type Flip-Flop

February 1990 Revised August 2000

100331 Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 k pull-down resistors.

Features
s 35% power reduction of the 100131 s 2000V ESD protection s Pin/function compatible with 100131 s Voltage compensated operating range -4.2V to -5.7V s Available to industrial grade temperature range

Ordering Code:
Order Number 100331SC 100331PC 100331QC 100331QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40 C to 85 C)

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Logic Symbol

Connection Diagrams
24-Pin DIP/SOIC

Pin Descriptions
Pin Names CP0 CP2 CPC D0 D2 CD0 CD2 SDn MR MS Q0-Q2 Q0 Q2 Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs 28-Pin PLCC

2000 Fairchild Semiconductor Corporation

DS010262

www.fairchildsemi.com