100351

100351 Low Power Hex D-Type Flip-Flop

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100351 Low Power Hex D-Type Flip-Flop

July 1988 Revised August 2000

100351 Low Power Hex D-Type Flip-Flop
General Description
The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 k pull-down resistors.

Features
s 40% power reduction of the 100151 s 2000V ESD protection s Pin/function compatible with 100151 s Voltage compensated operating range:

-4.2V to -5.7V
s Available to industrial grade temperature range

Ordering Code:
Order Number 100351SC 100351PC 100351QC 100351QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (-40 C to 85 C)

Devises also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Logic Symbol

Connection Diagrams
24-Pin DIP/SOIC

Pin Descriptions
Pin Names D0 D5 CPa, CPb MR Q0 Q5 Q0 Q5 Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs Description

28-Pin PLCC

2000 Fairchild Semiconductor Corporation

DS009885

www.fairchildsemi.com