100LVEL16

100LVEL16 3.3V ECL Differential Receiver

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100LVEL16 3.3V ECL Differential Receiver

January 2003 Revised February 2003

100LVEL16 3.3V ECL Differential Receiver
General Description
The 100LVEL16 is a low voltage differential receiver that contains an internally supplied voltage source, VBB. When used in a single ended input condition the unused input must be tied to VBB. When operating in this mode use a 0.01 F capacitor to decouple VBB and VCC and also limit the current sinking or sourcing capability to 0.5mA. When VBB is not used it should be left open. With inputs open the differential Q outputs default LOW and Q outputs default HIGH. The 100 series is temperature compensated.

Features
s Typical propagation delay of 300 ps s Typical IEE of 17 mA s Internal pull-down resistors on D s Fairchild MSOP-8 package is a drop-in replacement to ON TSSOP-8 s Meets or exceeds JEDEC specification EIA/JESD78 IC latch-up test s Moisture Sensitivity Level 1 s ESD Performance: Human Body Model 2000V Machine Model 150V

Ordering Code:
Product Order Number 100LVEL16M 100LVEL16M8 (Preliminary) Package M08A MA08D Code KVL16 KV16 Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Number Top Mark

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Connection Diagram

Logic Diagram

Top View

Pin Descriptions
Pin Name Q, Q D, D VBB VCC VEE NC Description ECL Data Outputs ECL Data Inputs Reference Voltage Positive Supply Negative Supply No Connect

2003 Fairchild Semiconductor Corporation

DS500776

www.fairchildsemi.com