100LVELT22

100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

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100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator

January 2003 Revised January 2003

100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
General Description
The 100LVELT22 is a LVTTL/LVCMOS to differential LVPECL translator operating from a single 3.3V supply. Both outputs of a differential pair should be terminated in 50 to VCC - 2.0V even if only one output is being used. If an output pair is unused both outputs can be left open (un-terminated). The 100 series is temperature compensated.

Features
s Typical propagation delay of 350 ps s 100 ps skew between outputs s Max ICC of 28 mA at 25 C s When TTL input is left Open Q output defaults HIGH s Fairchild MSOP-8 package is a drop-in replacement to ON TSSOP-8 s Flow through pinout s Meets or exceeds JEDEC specification EIA/JESD78 IC latch-up test s Moisture Sensitivity Level 1 s ESD Performance: Human Body Model 2000V Machine Model 200V

Ordering Code:
Product Order Number 100LVELT22M 100LVELT22M8 (Preliminary) Package M08A MA08D Code KVT22 KR22 Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Number Top Mark

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Connection Diagram

Logic Diagram

Top View

Pin Descriptions
Pin Name Qn, Qn D0 , D1 VCC GND Description LVPECL Differential Outputs LVTTL/LVCMOS Inputs Positive Supply Ground

2003 Fairchild Semiconductor Corporation

DS500777

www.fairchildsemi.com