74ABT16500

74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs

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74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs

April 1993 Revised January 1999

74ABT16500 18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16500 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the
resistor is determined by the current-sourcing capability of the driver.

Features
s Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode s Flow-through architecture optimizes PCB layout s Guaranteed latch-up protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability

Ordering Code:
Order Number 74ABT16500CSSC 74ABT16500CMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the letter suffix "X" to the ordering code.

Connection Diagram
Pin Assignment for SSOP

Function Table
OEAB L H H H H H H LEAB X H H L L L L

(Note 1) Output A X L H L H X X B Z L H L H B0 (Note 2) B0 (Note 3)

Inputs CLKAB X X X H L

Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.

1999 Fairchild Semiconductor Corporation

DS011581.prf

www.fairchildsemi.com