74ABT377

74ABT377 Octal D-Type Flip-Flop with Clock Enable

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74ABT377 Octal D-Type Flip-Flop with Clock Enable

January 1993 Revised November 1999

74ABT377 Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Features
s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus contention

Ordering Code:
Order Number 74ABT377CSC 74ABT377CSJ 74ABT377CMSA 74ABT377CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Connection Diagram

Pin Descriptions
Pin Names D0 D7 CE CP Q0 Q7 Descriptions Data Inputs Clock Enable (Active LOW) Clock Pulse Input Data Outputs

Truth Table
Operating Mode CP Load "1" Load "0" Hold (Do Nothing) Inputs Output Dn h I X X Qn H L No Change No Change

CE I I h H

H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Clock Transition h HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition I LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition

1999 Fairchild Semiconductor Corporation

DS011550

www.fairchildsemi.com