74AC109

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

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74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

March 2007

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop
Features
ICC reduced by 50% Outputs source/sink 24mA ACT109 has TTL-compatible inputs

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH

Ordering Information
Order Number
74AC109SC 74AC109SJ 74AC109MTC 74ACT109SC 74AC109MTC 74ACT109PC

Package Number
M16A M16D MTC16 M16A MTC16 N16E

Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number.

Connection Diagram

Pin Descriptions
Pin Names
J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2

Description
Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs

FACTTM is a trademark of Fairchild Semiconductor Corporation. 1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com