74F125

74F125 Quad Buffer (3-STATE)

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74F125 Quad Buffer (3-STATE)

April 1988 Revised September 2000

74F125 Quad Buffer (3-STATE)
Features
s High impedance base inputs for reduced loading

Ordering Code:
Order Number 74F125SC 74F125SJ 74F125PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Logic Symbol
IEEE/IEC

Connection Diagram

Unit Loading/Fan Out
U.L. Pin Names An, Bn On Description HIGH/LOW Inputs Outputs 1.0/0.033 Input IIH/IIL Output IOH/IOL 20 A/-20 A

600/106.6 (80) -12 mA/64 mA (48 mA)

Function Table
Inputs An L L H
H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial

Output Bn L H X O L H Z

2000 Fairchild Semiconductor Corporation

DS009475

www.fairchildsemi.com