74F377

74F377 Octal D-Type Flip-Flop with Clock Enable

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74F377 Octal D-Type Flip-Flop with Clock Enable

April 1988 Revised September 2000

74F377 Octal D-Type Flip-Flop with Clock Enable
General Description
The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Features
s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See 74F273 for master reset version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version

Ordering Code:
Order Number 74F377SC 74F377SJ 74F377PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

2000 Fairchild Semiconductor Corporation

DS009525

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