74F399

74F399 Quad 2-Port Register

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74F399 Quad 2-Port Register

April 1988 Revised January 2004

74F399 Quad 2-Port Register
General Description
The 74F399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock.

Features
s Select inputs from two data sources s Fully positive edge-triggered operation

Ordering Code:
Order Number 74F399SC 74F399SJ 74F399PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Logic Symbols

Connection Diagram

Unit Loading/Fan Out
U.L. Pin Names S CP I0a I0d I1a I1d Qa Qd Description HIGH/LOW Common Select Input Clock Pulse Input (Active Rising Edge) Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA

-1 mA/20 mA

2004 Fairchild Semiconductor Corporation

DS009533

www.fairchildsemi.com