74F533

74F533 Octal Transparent Latch with 3-STATE Outputs

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74F533 Octal Transparent Latch with 3-STATE Outputs

April 1988 Revised October 2000

74F533 Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted.

Features
s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373

Ordering Code:
Order Number 74F533SC 74F533SJ 74F533PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Logic Symbols
IEEE/IEC

Connection Diagram

2000 Fairchild Semiconductor Corporation

DS009548

www.fairchildsemi.com