74LVQ273

74LVQ273 Low Voltage Octal D-Type Flip-Flop

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74LVQ273 Low Voltage Octal D-Type Flip-Flop

February 1992 Revised June 2001

74LVQ273 Low Voltage Octal D-Type Flip-Flop
General Description
The LVQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

Features
s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 s 4 kV minimum ESD immunity

Ordering Code:
Order Number 74LVQ273SC 74LVQ273SJ 74LVQ273QSC Package Number M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions
Pin Names D0 D7 MR CP Q0 Q7 Description Data Inputs Master Reset Clock Pulse Input Data Outputs

2001 Fairchild Semiconductor Corporation

DS011358

www.fairchildsemi.com