74LVQ573

74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs

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74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs

February 1992 Revised June 2001

74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package.

Features
s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 s 4 kV minimum ESD immunity

Ordering Code:
Order Number 74LVQ573SC 74LVQ573SJ 74LVQ573QSC Package Number M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Truth Table
Inputs Outputs D H L X X On H L O0 Z

Pin Descriptions
Pin Names D0 D7 LE OE O0 O7 Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs Description

OE L L L H

LE H H L X

H HIGH Voltage L LOW Voltage Z High Impedance X Immaterial O0 Previous O0 before HIGH-to-LOW transition of Latch Enable

2001 Fairchild Semiconductor Corporation

DS011361

www.fairchildsemi.com