74LVX112

74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear

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74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear

October 1996 Revised December 2003

74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear
General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs (J, K, PRESET, CLEAR, and CLOCK) and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. Clear and Preset are independent of the clock and are accomplished by a low logic level on the corresponding input. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

Features
s Input voltage level translation from 5V 3V s Ideal for low power/low noise 3.3V applications

Ordering Code:
Order Number 74LVX112M 74LVX112SJ 74LVX112MTC Package Number M16A M16D MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

Connection Diagram

Pin Descriptions
Pin Names J1, J2, K1, K2 CLK1, CLK2 CLR1, CLR2 PR1, PR2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling edge) Direct Clear Inputs (Active LOW) Direct Preset Inputs (Active LOW) Description

2003 Fairchild Semiconductor Corporation

DS012158

www.fairchildsemi.com