74LVX125

74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs

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74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs

February 1994 Revised February 2005

74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs
General Description
The LVX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

Features
s Input voltage level translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance

Ordering Code:
Order Number 74LVX125M 74LVX125SJ 74LVX125MTC 74LVX125MTCX NL (Note 1) Package Number M14A M14D MTC14 MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: " NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol
IEEE/IEC

Connection Diagram

Truth Table Pin Descriptions
OEn Pin Names An OEn On Description Inputs Output Enable Inputs Outputs L L H
H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial

Inputs An L H X

Output On L H Z

2005 Fairchild Semiconductor Corporation

DS012007

www.fairchildsemi.com