74LVX373

74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs

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74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs

June 1993 Revised April 2005

74LVX373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
General Description
The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.

Features
s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance

Ordering Code:
Order Number 74LVX373M 74LVX373SJ 74LVX373MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDED J-STD-020B.

Logic Symbols

Pin Descriptions
Pin Names D0 D7 LE OE Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Description

IEEE/IEC

O0 O7

Truth Table
Inputs LE X H OE H L L L Dn X L H X Outputs On Z L H O0

Connection Diagram
H L Z X O0

H L

HIGH Voltage Level LOW Voltage Level High Impedance Immaterial Previous O0 before HIGH-to-LOW transition of Latch Enable

2005 Fairchild Semiconductor Corporation

DS011613

www.fairchildsemi.com