74VHC125

74VHC125 Quad Buffer with 3-STATE Outputs

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74VHC125 Quad Buffer with 3-STATE Outputs

May 2007

74VHC125 Quad Buffer with 3-STATE Outputs
Features
High Speed: tPD 3.8ns (Typ.) at VCC 5V Lower power dissipation: ICC 4 A (Max.) at

General Description
The VHC125 contains four independent non-inverting buffers with 3-STATE outputs. It is an advanced highspeed CMOS device fabricated with silicon gate CMOS technology and achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

TA 25 C

High noise immunity: VNIH VNIL 28% VCC (Min.) Power down protection is provided on all inputs Low noise: VOLP 0.8V (Max.) Pin and function compatible with 74HC125

Ordering Information
Order Number
74VHC125M 74VHC125MX NL(1) 74VHC125SJ 74VHC125MTC 74VHC125MTCX NL(1)

Package Number
M14A M14A M14D MTC14 MTC14

Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. Pb-Free package per JEDED J-STD-020B. Note: 1. Device available in Tape and Reel only.

1993 Fairchild Semiconductor Corporation 74VHC125 Rev. 1.3

www.fairchildsemi.com