DM74ALS109A

DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear

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DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear

April 1984 Revised February 2000

DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input J or K is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the J, K input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. The J-K design allows operation as a D flip-flop by tying the J and K inputs together.

Features
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible with Schottky and LS TTL counterpart s Improved AC performance over LS109 at approximately half the power

Ordering Code:
Order Number DM74ALS109AM DM74ALS109AN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.

Connection Diagram

Function Table
Inputs PR L H L H H H H H CLR H L L H H H H H CK X X X L J X X X L H L H X K X X X L L H H X Q0 H Q0 Q H L H (Note 1) L TOGGLE Q0 L Q0 Outputs Q L H H (Note 1) H

L LOW State H HIGH State X Don t Care Positive Edge Transition, Q0 Previous Condition of Q Note 1: This condition is nonstable; it will not persist when present and clear inputs return to their inactive (HIGH) level. The output levels in this condition are not guaranteed to meet the VOH specification.

2000 Fairchild Semiconductor Corporation

DS006196

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