DM74ALS175

DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear

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DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear

May 2007

DM74ALS174, DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Features
Advanced oxide-isolated ion-implanted Schottky

General Description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

TTL process Pin and functional compatible with LS family counterpart Typical clock frequency maximum is 80MHz Switching performance guaranteed over full temperature and VCC supply range

Ordering Information
Ordering Code
DM74ALS174M DM74ALS174SJ DM74ALS175M DM74ALS175SJ DM74ALS175N

Package Number
M16A M16D M16A M16D N16E

Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering number.

1986 Fairchild Semiconductor Corporation DM74ALS174, DM74ALS175 Rev. 1.2

www.fairchildsemi.com