DM74ALS5245 Octal 3-STATE Transceiver

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

DM74ALS5245 Octal 3-STATE Transceiver

June 2007

DM74ALS5245 Octal 3-STATE Transceiver
Features
Input Hysteresis Low output noise generation High input noise immunity Advanced oxide-isolated, ion implanted Schottky

tm

General Description
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The inputs include hysteresis which provides improved noise rejection. Data is transmitted either from the A bus to the B bus or from the B bus to the A bus depending on the logic level of the direction control (DIR) input. The device can be disabled via the enable input (G) which causes the outputs to enter the high impedance mode so the buses are effectively isolated.

TTL process Switching specification guaranteed over the full temperature and VCC range PNP inputs to reduce input loading

Ordering Information
Order Number
DM74ALS5245WM DM74ALS5245SJ

Package Number
M20B M20D

Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering number.

Connection Diagram

Function Table
Control Inputs G
L L H L LOW Logic Level
1986 Fairchild Semiconductor Corporation DM74ALS5245 Rev. 1.2

DIR
L H X H HIGH Logic Level

Operation
B Data to A Bus A Data to B Bus High Impedance X Don t Care (Either LOW or HIGH Logic Level)
www.fairchildsemi.com

DM74ALS5245 Datasheet Fairchild Download PDF

Add this permalink to your bookmarks for future download of DM74ALS5245 datasheet

Permalink: http://datasheet.emcelettronica.com/fairchild/DM74ALS5245

DM74ALS5245 DATASHEET