September 2001

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September 2001

FDC6301N Dual N-Channel , Digital FET
General Description
These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, these N-Channel FET s can replace several digital transistors, with a variety of bias resistors.

Features
25 V, 0.22 A continuous, 0.5 A Peak. RDS(ON) 5 VGS 2.7 V RDS(ON) 4 VGS 4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) 1.5V. Gate-Source Zener for ESD ruggedness. 6kV Human Body Model.

SOT-23

TM SuperSOT -6

TM SuperSOT -8

SO-8

SOT-223

SOIC-16

Mark: .301

INVERTER APPLICATION

Vcc

4

3

D

OUT

5 6

2
IN G S GND

1

Absolute Maximum Ratings
Symbol VDSS, VCC VGSS, VIN ID, IOUT PD TJ,TSTG ESD Parameter

TA 25oC unless other wise noted FDC6301N 25 - 0.5 to 8 Units V V A

Drain-Source Voltage, Power Supply Voltage Gate-Source Voltage, VIN Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b)

0.22 0.5 0.9 0.7 -55 to 150 6.0

W

Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm)

C kV

THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)

140 60

C/W C/W
FDC6301N Rev.D

2001 Fairchild Semiconductor Corporation

FDC6301N Datasheet Fairchild Download PDF

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FDC6301N DATASHEET