July 1997

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July 1997

FDC6304P Digital FET, Dual P-Channel
General Description
These P-Channel enhancement mode field effect transistor are produced using Fairchild s proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance at low gate drive conditions. This device is designed especially for application in battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts.

Features
-25 V, -0.46 A continuous, -1.0 A Peak. RDS(ON) 1.5 VGS -2.7 V RDS(ON) 1.1 VGS -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) 1.5 V. Gate-Source Zener for ESD ruggedness. 6kV Human Body Model.

SOT-23

SuperSOTTM-6 Mark: .304

SuperSOTTM-8

SO-8

SOT-223

SOIC-16

4

3

5

2

6

1

Absolute Maximum Ratings
Symbol VDSS VGSS ID PD TJ,TSTG ESD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current

TA 25oC unless other wise noted FDC6304P -25 -8 Units V V A

- Continuous - Pulsed

-0.46 -1
(Note 1a) (Note 1b)

Maximum Power Dissipation

0.9 0.7 -55 to 150 6.0

W

Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm)

C kV

THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)

140 60

C/W C/W
FDC6304P Rev.D

1997 Fairchild Semiconductor Corporation

FDC6304P Datasheet Fairchild Download PDF

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FDC6304P DATASHEET