FDS6812A

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FDS6812A

November 2001

FDS6812A
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
General Description
These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required.

Features
6.7 A, 20 V. RDS(ON) 22 m VGS 4.5 V RDS(ON) 35 m VGS 2.5 V

Low gate charge (12 nC typical) High performance trench technology for extremely low RDS(ON) High power and current handling capability

D2 D

D2 D

DD1 D1 D

5 6 7
Q1

4 3 2
Q2

SO-8
Pin 1 SO-8
G2 S2 S

G1 S1 G

S

8

1

S

Absolute Maximum Ratings
Symbol
VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current Continuous Pulsed

TA 25 C unless otherwise noted

o

Parameter

Ratings
20 12
(Note 1a)

Units
V V A W

6.7 35 2

Power Dissipation for Dual Operation Power Dissipation for Single Operation
(Note 1a) (Note 1b) (Note 1c)

1.6 1 0.9 55 to 150 C

TJ, TSTG

Operating and Storage Junction Temperature Range

Thermal Characteristics
RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)

78 40

C/W C/W

Package Marking and Ordering Information
Device Marking FDS6812A Device FDS6812A Reel Size 13 Tape width 12mm Quantity 2500 units

2001 Fairchild Semiconductor Corporation

FDS6812A Rev B (W)

FDS6812A Datasheet Fairchild Download PDF

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FDS6812A DATASHEET