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FDS8928A

By datasheet - April 3rd, 2008

July 1998

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July 1998

FDS8928A Dual N P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N- and P -Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

Features
N-Channel 5.5 A,30 V, RDS(ON) 0.030 VGS 4.5 V RDS(ON) 0.038 VGS 2.5 V. P-Channel -4 A,-20 V, RDS(ON) 0.055 VGS -4.5 V RDS(ON) 0.072 VGS -2.5 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual (N P-Channel) MOSFET in surface mount package.

SOT-23

SuperSOTTM-6

SuperSOTTM-8

SO-8

SOT-223

SOIC-16

D2 D1 D1 D2

5 6 7

4 3 2 1

S FD 8A 2 89
S2 G2 G1

8

SO-8

pin 1

S1

Absolute Maximum Ratings
Symbol VDSS VGSS ID Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed PD

T A 25 C unless otherwise noted

N-Channel 30 8
(Note 1a)

P-Channel -20 -8 -4 -20 2

Units V V A

5.5 20

Power Dissipation for Dual Operation Power Dissipation for Single Operation
(Note 1a) (Note 1b) (Note 1c)

W

1.6 1 0.9 -55 to 150 C

TJ,TSTG

Operating and Storage Temperature Range

THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)

78 40

C/W C/W

1998 Fairchild Semiconductor Corporation

FDS8928A Rev. B

FDS8928A Datasheet Fairchild Download PDF

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