FIN1018

FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver

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FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver

March 2001 Revised April 2002

FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver
General Description
This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1018 can be paired with its companion driver, the FIN1017, or with any other LVDS driver.

Features
s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout s 8-Lead SOIC and US-8 packages save space

Ordering Code:
Order Number FIN1018M FIN1018MX FIN1018K8X Package Number M08A M08A MAB08A Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL]

Pin Descriptions
Pin Name ROUT RIN RIN- VCC GND NC Description LVTTL Data Output Non-inverting Driver Input Inverting Driver Input Power Supply Ground No Connect

Connection Diagrams
8-Lead SOIC

Function Table
Input RIN L H RIN- H L Outputs ROUT L H H

Pin Assignment for US-8 Package

Fail Safe Condition
H HIGH Logic Level L LOW Logic Level Fail Safe Open, Shorted, Terminated

TOP VIEW

2002 Fairchild Semiconductor Corporation

DS500502

www.fairchildsemi.com