FIN1101

FIN1101 LVDS Single Port High Speed Repeater

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FIN1101 LVDS Single Port High Speed Repeater

January 2002 Revised September 2002

FIN1101 LVDS Single Port High Speed Repeater
General Description
This single port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. It accepts and outputs LVDS levels with a typical differential output swing of 330 mV which provides low EMI at ultra low power dissipation even at high frequencies. It can directly accept multiple differential I/O including: LVPECL, HSTL, and SSTL-2 for translating directly to LVDS.

Features
s Up to 1.6 Gb/s full differential path s 3.5 ps max random jitter and 135 ps max deterministic jitter s 3.3V power supply operation s Wide rail-to-rail common mode range s Ultra low power consumption s LVDS receiver inputs accept LVPECL, HSTL, and SSTL-2 directly s Power off protection s 7 kV HBM ESD protection (all pins) s Meets or exceed the TA/EIA-644-A LVDS standard s Packaged in 8-pin SOIC and US8 s Open circuit fail safe protection

Ordering Code:
Order Number FIN1101M FIN1101MX FIN1101K8X Package Number M08A M08A MAB08A Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL]

Connection Diagrams
SOIC Package

Pin Descriptions
Pin Name RIN RIN- DOUT DOUT- EN VCC Description Non-Inverting LVDS Inputs Inverting LVDS Inputs Non-Inverting Driver Outputs Inverting Driver Outputs Driver Enable Pin Power Supply Ground

US8 Package

GND

Function Table
Inputs EN H H H L
H HIGH Logic Level X Don t Care

Outputs RIN- L H X DOUT H L H Z DOUT- L H L Z

RIN H L X

Functional Diagram

Fail Safe Case

L LOW Logic Level Z High Impedance

2002 Fairchild Semiconductor Corporation

DS500654

www.fairchildsemi.com