GTLP18T612

GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver

May 1999 Revised July 2002

GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP s reduced output swing ( 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild s GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.

Features
s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -24mA/ 24mA s B Port sink 50mA s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Ordering Code:
Order Number GTLP18T612G (Note 1)(Note 2) GTLP18T612MEA (Note 2) GTLP18T612MTD (Note 2) Package Number BGA54A MS56A MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Note 1: Ordering code "G" indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.

2002 Fairchild Semiconductor Corporation

DS500169

www.fairchildsemi.com