LTC2221| Datasheet

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LTC2220/LTC2221 12-Bit,170Msps/ 135Msps ADCs

FEATURES

DESCRIPTIO

Sample Rate: 170Msps/135Msps 67.5dB SNR up to 140MHz Input 80dB SFDR up to 170MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 890mW/660mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: 0.5V or 1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 185Msps: LTC2220-1 (12-Bit) 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) 64-Pin 9mm 9mm QFN Package

The LTC 2220 and LTC2221 are 170Msps/135Msps, sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2220/ LTC2221 are perfect for demanding communications applications with AC performance that includes 67.5dB SNR and 80dB spurious free dynamic range for signals up to 170MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include 0.4LSB INL (typ), 0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC inputs may be driven differentially or single ended with a sine wave, PECL, LVDS
, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

APPLICATIO S

Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment

, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO
3.3V REFH REFL FLEXIBLE REFERENCE

VDD 0.5V TO 3.6V OVDD

100 90 4th OR HIGHER
SFDR (dBFS)

+
ANALOG INPUT INPUT S/H

12-BIT PIPELINED ADC CORE

CORRECTION LOGIC

OUTPUT DRIVERS

D11 D0

80 70 2nd OR 3rd 60 50

CMOS OR LVDS

OGND CLOCK/DUTY CYCLE CONTROL
22201 TA01

40

ENCODE INPUT

U
SFDR vs Input Frequency
0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22201 TA01b
22201fa

U

U

1

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LTC2221 DATASHEET