54F64| Datasheet

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54F 74F64 4-2-3-2-Input AND-OR-Invert Gate

November 1994

54F 74F64 4-2-3-2-Input AND-OR-Invert Gate
General Description
This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function

Commercial 74F64PC

Military

Package Number N14A

Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C

54F64DM (Note 2) 74F64SC (Note 1) 54F64FM (Note 2) 54F64LM (Note 2)
Note 1 Devices also available in 13

J14A M14A W14B E20A

reel Use suffix e SCX

Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB

Logic Symbol
IEEE IEC

Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC

TL F 9467 2 TL F 9467 1

TL F 9467 3

Unit Loading Fan Out
54F 74F Pin Names Description UL HIGH LOW 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA b 1 mA 20 mA

An Bn Cn Dn O

Inputs Output

TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation

TL F 9467

RRD-B30M105 Printed in U S A

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54F64 DATASHEET