ADC12C170| Datasheet

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ADC12C170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs

August 2007

ADC12C170 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS Outputs
General Description
The ADC12C170 is a high-performance CMOS analog-todigital converter capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 1.1 GHz. The ADC12C170 operates from dual +3.3V and +1.8V power supplies and consumes 715 mW of power at 170 MSPS. The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 5 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time. The differential inputs provide a full scale differential input swing equal to 2 times the refer
ence voltage. A stable 1.0V internal voltage reference is provided, or the ADC12C170 can be operated with an external reference. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. The ADC12C170 is pin compatible with the ADC14155, ADC11C125 and ADC11C170. It is available in a 48-lead LLP package and operates over the industrial temperature range of -40 C to +85 C.

Features

1.1 GHz Full Power Bandwidth Internal sample-and-hold circuit Low power consumption Internal precision 1.0V reference Single-ended or Differential clock modes Clock Duty Cycle Stabilizer Dual +3.3V and +1.8V supply operation Power-down and Sleep modes Offset binary or 2's complement output data format Pin-compatible: ADC14155, ADC11C125, ADC11C170 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

Key Specifications

Resolution Conversion Rate SNR (fIN = 70 MHz) SFDR (fIN = 70 MHz) ENOB (fIN = 70 MHz) Full Power Bandwidth Power Consumption 12 Bits 170 MSPS 67.2 dBFS (typ) 85.4 dBFS (typ) 10.8 bits (typ) 1.1 GHz (typ) 715 mW (typ)

Applications

High IF Sampling Receivers Wireless Base Station Receivers Power Amplifier Linearization Multi-carrier, Multi-mode Receivers Test and Measurement Equipment Communications Instrumentation Radar Systems

Block Diagram

20209202

2007 National Semiconductor Corporation

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