DS90LV110T| Datasheet

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

DS90LV110T 1 to 10 LVDS Data/Clock Distributor

May 2007

DS90LV110T 1 to 10 LVDS Data/Clock Distributor
General Description
DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz. The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the Application Information section of this datasheet.

Features
Low jitter 800 Mbps fully differential data path 145 ps (typ) of pk-pk jitter with PRBS = 223-1 data pattern
at 800 Mbps Single +3.3 V Supply Less than 413 mW (typ) total power dissipation Balanced output impedance Output channel-to-channel skew is 35ps (typ) Differential output voltage (VOD) is 320mV (typ) with 100 termination load. LVDS receiver inputs accept LVPECL signals Fast propagation delay of 2.8 ns (typ) Receiver input threshold < 100 mV 28 lead TSSOP package Conforms to ANSI/TIA/EIA-644 LVDS standard

Connection Diagram

Block Diagram

10133701 10133705

Order Number DS90LV110ATMT See NS Package Number MTC28

2007 National Semiconductor Corporation

101337

www.national.com