74ALVT16260_3| Datasheet

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74ALVT16260
12-bit to 24-bit multiplexed D-type latches; 3-state
Rev. 03 -- 20 March 2006 Product data sheet

1. General description
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is also useful in memory-interleaving applications. Three 12-bit I/O ports (A1 to A12, 1B1 to 1B12 and 2B1 to 2B12) are available for address or data transfer. The output enable inputs (OE1B, OE2B, and OEA) control the bus transceiver functions. OE1B and OE2B also allow bank control in the A to B direction. Address or data information can be stored using the internal storage latches. The latch enable inputs (LE1B, LE2B, LEA1B and LEA2B) are used to control data storage. When the latch enable input is HIGH, the latch is transparent. When the latch enable input goes LOW, the data present at the inputs is latched and remains latched until the latch enable input is returned HIGH. To
ensure the high-impedance state during power-up or power-down, all output enable inputs should be tied to VCC through a pull-up resistor. The minimum value of the resistor is determined by the current sinking capability of the driver. The 74ALVT16260 is available in a SSOP56 and a TSSOP56 package.

2. Features
I I I I I I I I 5 V I/O compatible Bus hold inputs eliminate the need for external pull-up resistors Live insertion and extraction permitted Power-up 3-state Power-up reset Output capability: +64 mA and -32 mA Distributed VCC and GND pin configuration minimizes high-speed switching noise Latch-up protection: N JESD78: exceeds 500 mA I ESD protection: N MIL STD 883C, method 3015: exceeds 2000 V N Machine model: exceeds 200 V