74ALVT16823_4| Datasheet

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74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
Rev. 04 -- 2 August 2005 Product data sheet

1. General description
The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and master reset (pin nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop. It is designed for VCC operation from 2.5 V to 3.0 V with I/O compatibility to 5 V.

2. Features
s Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops s 5 V I/O compatible s Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors s Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion and extraction permitted s Power-up 3-state s Power-up reset s No bus current loading when output is tied to 5 V bus s Output capability: +64 mA to -32 mA s Latch-up protection: x JESD78: exceeds 500 mA s ESD protection: x MIL STD 883, method 3015: exceeds 2000 V x Machine Model: exceeds 200 V