74AUP1G18_1| Datasheet

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74AUP1G18
Low-power 1-of-2 demultiplexer with 3-state deselected output
Rev. 01 -- 13 October 2006 Product data sheet

1. General description
The 74AUP1G18 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G18 provides a 1-of-2 non-inverting demultiplexer with 3-state output. The 74AUP1G18 buffers the data on input pin (A) and passes it either to output 1Y or 2Y, depending on whether the state of the select input pin (S) is LOW or HIGH.

2. Features
I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114-D Class 3A exceeds 4000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static power consumption; ICC = 0.9 uA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from -40 C to +85 C and -40 C to +125 C