74AUP1T45_1| Datasheet

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74AUP1T45
Low-power dual supply translating transceiver; 3-state
Rev. 01 -- 18 October 2006 Product data sheet

1. General description
The 74AUP1T45 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outp
ut, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND, both A and B are in the high-impedance OFF-state.

2. Features
I Wide supply voltage range: N VCC(A): 1.1 V to 3.6 V N VCC(B): 1.1 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114-D Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static power consumption; ICC = 0.9 uA (maximum) I Suspend mode I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation