74AUP1Z125_1| Datasheet

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74AUP1Z125
Low-power X-tal driver with enable and internal resistor
Rev. 01 -- 3 August 2006 Product data sheet

1. General description
The 74AUP1Z125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. When not in use the EN input can be driven HIGH, pulling up the X1 input and putting the device in a low power disable mode. Schmitt-trigger action at the EN input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF at output Y. The IOFF circuitry disables the output Y, preventing the damaging backflow current through the device when it is powered down. The 74AUP1Z125 combines the functions of the 74AUP1GU04 and 74AUP1G125 to provide a device optimized for use in crystal oscillator applications. The integration of the two devices into the 74AUP1Z125 produces the benefits of a compact footprint, lower power dissipation and
stable operation over a wide range of frequency and temperature.

2. Features
s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s ESD protection: x HBM JESD22-A114-C Class 3A. Exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 uA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation at output Y s Multiple package options s Specified from -40 C to +85 C and -40 C to +125 C