74HC21_3| Datasheet

By datasheet - May 14th, 2008

74HC21_3| Datasheet

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74HC21
Dual 4-input AND gate
Rev. 03 -- 12 November 2004 Product data sheet

1. General description
The 74HC21 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC21 is specified in compliance with JEDEC standard no. 7A. The 74HC21 provide the 4-input AND function.

2. Features
s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from -40 C to +80 C and from -40 C to +125 C.

3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol tPHL, tPLH CI CPD
[1]

Parameter propagation delay nA, nB, nC, nD to nY input capacitance power dissipation capacitance

Conditions CL = 15 pF; VCC = 5 V VI = GND to VCC
[1]

Min -

Typ 10 3.5 15

Max -

Unit ns pF pF

CPD is used to determine the dynamic power dissipation (PD in uW). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.