74HC258_3| Datasheet

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74HC258
Quad 2-input multiplexer; 3-state; inverting
Rev. 03 -- 12 November 2004 Product data sheet

1. General description
The 74HC258 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC258 is specified in compliance with JEDEC standard no. 7A. The 74HC258 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and is controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in inverted form from the select inputs. The 74HC258 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high-impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE ( 1I1 S + 1I0 S ) 2Y = OE ( 2I1 S + 2I0 S ) 3Y = OE ( 3I1 S + 3I0 S ) 4Y = OE ( 4I1 S + 4I0 S ) The 74HC258 is identical to the 74HC257 but has inver
ting outputs.

2. Features
s s s s s 3-state outputs interface directly with system bus Low-power dissipation Inverting data path Complies with JEDEC standard no. 7A ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from -40 C to +80 C and from -40 C to +125 C.