74HC564_3| Datasheet

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74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 -- 11 November 2004 Product data sheet

1. General description
The 74HC564 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC564 is specified in compliance with JEDEC standard no. 7A. The 74HC564 is a octal D-type flip-flop featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74HC564 is functionally identical to the 74HC574 but has inverting outputs. The 74HC564 is functionally identical to the 74HC534, but has a different pinning.

2. Features
s s s s s s s 3-state inverting outputs for bus oriented applications 8-bit positive-edge triggered register Common 3-state output enable input Independent register and 3-state buffer operation Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from -40 C to +80 C and from -40 C to +125 C.