74HC590_1| Datasheet

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74HC590
8-bit binary counter with output register; 3-state
Rev. 01 -- 30 March 2005 Product data sheet

1. General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of
the register.

2. Features
s s s s s Counter and register have independent clock inputs Counter has master reset Complies with JEDEC standard no. 7A Multiple package options ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V x CDM EIA/JESD22-C101C exceeds 2000 V s Specified from -40 C to +80 C and from -40 C to +125 C

3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns Symbol tPHL, tPLH Parameter Conditions Min Typ 19 17 18 13 Max Unit ns ns ns ns propagation delay CPC to CL = 50 pF; VCC = 4.5 V RCO propagation delay CPR to CL = 50 pF; VCC = 4.5 V Qn tPLH tPZH, tPZL propagation delay MRC to CL = 50 pF; VCC = 4.5 V RCO 3-state output enable time CL = 50 pF; VCC = 4.5 V OE to Qn